The present invention relates to a method of manufacturing a semiconductor device, more specifically, a method of manufacturing a semiconductor device in which silicidation is made, and a method of manufacturing a semiconductor device in which a contact plug is formed, connected to a metal silicide film.
As art of making a gate electrode and source/drain diffused layers with low resistivity, the process of forming metal silicide films on the surfaces of them by self-alignment, the so-called salicide (Self-Aligned Silicide) process is known. As metal materials to be reacted with silicon in the salicide process, cobalt (Co), titanium (Ti), nickel (Ni), etc. are known. Among them, nickel silicide is much noted for its advantages of stabilizing the resistance of the gate electrode even when the gate electrode is downsized, etc.
Furthermore, as for nickel silicide, Non-Patent Reference 1 reports that platinum (Pt) is added to nickel silicide to thereby improve the thermal stability.
The nickel silicide with a metal improving the thermal stability such as Pt or others added is formed by silicidation process using a Ni alloy film of an alloy of Ni and a metal such as Pt or others.
In the silicidation process using the Ni alloy film, a Ni alloy film is deposited on a gate electrode and source/drain diffused layers. Then, as required, a protective film of a titanium nitride (TiN) film or others, is deposited on the Ni alloy film.
Then, as the first thermal processing for the silicidation, thermal processing of a relatively low temperature of below 300° C. including 300° C. is made to form silicide films of 2:1 composition ratio of Ni alloy vs. Si ((Ni alloy)2Si films) on the gate electrode and the source/drain diffused layers.
Then, the protective film, and the unreacted part of the Ni alloy film are selectively removed by wet etching.
Then, as the second thermal processing for the silicidation, thermal processing of a relatively high temperature of 300-400° C. is made to thereby form nickel alloy monosilicide films of low resistance on the gate electrodes and the source/drain diffused layers.
On a transistor with the metal silicide films formed on the gate electrode and the source/drain diffused layers by salicide process, an inter-layer insulating film is formed. In the inter-layer insulating film, contact holes are formed down to the metal silicide films. In the contact holes, contact plugs are buried, connected to the metal silicide films. Interconnections formed on the interlayer insulating film are connected, via the contact plugs, to the metal silicide films formed on the gate electrode and the source/drain diffused layers.
Generally, the contact plug is formed of a barrier metal formed in the contact hole, and a buried metal of tungsten or others, buried in the contact hole with the barrier metal formed in (refer to, e.g., Patent References 12 to 14). The barrier metal is formed for stabilizing the contact resistance with respect to the metal silicide film and suppressing the reaction between the metal silicide film and the buried metal and the diffusion of the buried metal. The barrier metal functions also as the adhesion layer for improving the adhesion to the metal silicide film.
Related arts are disclosed in, e.g., Patent References 1 to 14 and Non-Patent References 1 to 10 as listed below.    Patent Reference 1: Japanese published unexamined patent application No. 2002-124487    Patent Reference 2: Japanese published unexamined patent application No. 2005-19943    Patent Reference 3: Japanese published unexamined patent application No. 2005-19515    Patent Reference 4: Japanese translation of PCT international application No. Hei 5-500735    Patent Reference 5: Japanese published unexamined patent application No. 2002-118078    Patent Reference 6: Japanese examined patent application publication No. Hei 7-70498    Patent Reference 7: Japanese published unexamined patent application No. 2004-356431    Patent Reference 8: Japanese published unexamined patent application No. 2002-367929    Patent Reference 9: Japanese published unexamined patent application No. 2006-13284    Patent Reference 10: Japanese published unexamined patent application No. 2002-151428    Patent Reference 11: Japanese published unexamined patent application No. 2005-11891    Patent Reference 12: Japanese published unexamined patent application No. 2005-129831    Patent Reference 13: Japanese published unexamined patent application No. Hei 9-205070    Patent Reference 14: Japanese published unexamined patent application No. Hei 8-213343    Non-Patent Reference 1: D. Mangelinck et al., “Effect of Co, Pt, and Au additions on the stability and epitaxy of NiSi2 films on (111)Si”, J. Appl. Phys., Vol. 84, No. 5, pp. 2583-2590 (1998)    Non-Patent Reference 2: V. Teodorescu et al., “In situ transmission electron microscopy study of Ni silicide phases formed on (001) Si active lines”, J. Appl. Phys., Vol. 90, No. 1, pp. 167-174 (2001)    Non-Patent Reference 3: J. P. Sullivan et al., “Control of interfacial morphology: NiSi2/Si(100)”, J. Appl. Phys., Vol. 72, No. 2, pp. 478-489 (1992)    Non-Patent Reference 4: Y.-J. Chang et al., “Diffusion layers and the Schottky-barrier height in nickel silicide-silicon interfaces”, Phys. Rev. B, vol. 28, No. 10, pp. 5766-5773 (1983)    Non-Patent Reference 5: M. G. Grimaldi et al., “Epitaxial NiSi2 formation by pulsed laser irradiation of thin Ni layers deposited on Si substrates”, Appl. Phys. Lett., Vol. 43, No. 3, pp. 244-246 (1983)    Non-Patent Reference 6: Y.-W. Ok et al., “Field emission from Ni-disilicide nanorods formed by using implantation of Ni in Si coupled with laser annealing”, Appl. Phys. Lett., Vol. 88, 043106 (2006)    Non-Patent Reference 7: B. I. Boyanov et al., “Growth of epitaxial CoSi2 on SiGe(001)”, J. Appl. Phys., Vol. 86, No. 3, pp. 1355-1362 (1999)    Non-Patent Reference 8: P. Baeri et al., “Epitaxial NiSi layers on <111>-oriented Si obtained by pulsed laser irradiation”, J. Appl. Phys., Vol. 66, No. 2, pp. 861-866 (1989)    Non-Patent Reference 9: F. L. Chow et al., “Pulsed laser-induced silicidation on TiN-capped Co/Si bilayers”, J. Appl. Phys., Vol. 99, 044902 (2006)    Non-Patent Reference 10: K. Kawamura et al., “Dependence of CoSi2 Sheet Resistance on Cobalt Thickness for Gate Lengths of 50 nm or Less”, Jpn. J. Appl. Phys., Vol. 45, No. 5A, pp. 3972-3975 (2006)
However, platinum is solved generally only in aqua regia, which is a solution of concentrated hydrochloric acid and concentrated nitric acid mixed by about 3:1 volume ratio. Accordingly, when a nickel platinum film used in the silicidation is removed by the same process as a nickel film without platinum added, the platinum resides on the substrate. The platinum residue affects the characteristics of MOS transistors, etc. formed on the substrate.
When the nickel platinum film is removed with aqua regia, which is very corrosive, a chemical liquid treating apparatus and a waste liquid treating apparatus specialized for aqua regia are necessary.
In forming the nickel silicide film on the source/drain diffused layer of a transistor, when the gate width W of the transistor is as small as, e.g., below 1 μm including 1 μm, nickel disilicide (NiSi2) crystals grow in spikes below the silicide film down near the junction part of the source/drain diffused layer, and the junction leak current is often increased. Even in using a Ni alloy film, such as a NiPt film or others, for the silicidation, it is often difficult to suppress the growth of the NiSi2 crystals in spikes.
When the silicidation using a Ni film or a Ni alloy film is made, low-temperature process must be used so as to suppress the agglomeration of the silicide film. However, when the barrier metal forming the contact plugs are formed by the conventional deposition process, the contact resistance is increased, and the scatter of the contact resistance is often increased.